Embedded {hardware} specialist Renesas has introduced its first totally in-house processor core primarily based on the free and open RISC-V instruction set structure (ISA) — marking a transfer away from utilizing third-party core designs, together with these from business large Arm.

“The rising recognition of the RISC-V ISA inside the semiconductor business is a boon for innovation. It supplies designers with unprecedented flexibility and can slowly however steadily problem and remodel the present panorama of embedded programs,” Renesas’ Giancarlo Parodi says of the expertise behind the corporate’s newest microcontroller. “Previously, Renesas has embraced RISC-V expertise introducing 32-bit ASSP gadgets for voice-control and motor-control constructed on CPU cores developed by Andes Expertise Corp. The thrilling subsequent step is the supply of [our] first in-house engineered CPU core.”

Whereas Renesas is not sharing full product particulars on the elements which can use its in-house core but, it has confirmed a number of technical particulars concerning the core itself. A block diagram exhibits a single 32-bit RISC-V core with performance-boosting dynamic department predictor, a {hardware} multiplier/divider, a vectored interrupt controller, a stack monitor register, separate instruction and knowledge buses ,and compact JTAG (cJTAG)/JTAG debug capabilities. It has additionally promised a 3.27 CoreMark per megahertz (CoreMark/MHz) efficiency stage — although at an as-yet unknown clock pace.

“This CPU is appropriate for a lot of totally different software contexts. It may be used as primary CPU or to handle an on-chip subsystem and even to be embedded in a specialised ASSP [Application-Specific Standard Product] system,” Parodi claims. “Clearly it is extremely versatile. Second, the implementation could be very environment friendly when it comes to silicon space, which helps scale back working present and leakage present throughout standby time, moreover the plain impact of smaller value affect. Third, regardless of concentrating on small embedded programs, it supplies a surprisingly excessive stage of computational throughput to meet the more and more demanding efficiency requirement of even deeply embedded purposes.”

The core makes use of the free and open RISC-V instruction set structure, together with a number of of its extensions: Parodi says the core implements the RV32I or RV32E ISA with multiplication (M), atomic entry (A), compressed directions (C), and bit-manipulation (B) extensions. “That is the great thing about the RISC-V ISA idea,” Parodi claims, “constructed from the ground-up to permit the designer to decide on which components to incorporate within the processor, depending on their goal use case, and consequently optimize the trade-off between the ensuing energy consumption, efficiency, and silicon footprint.”

Renesas says it’s sampling silicon with the brand new core to “choose prospects” now, with the primary industrial chips attributable to launch within the first quarter of subsequent yr. Extra info is out there in Parodi’s weblog publish.