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Chinese language embedded electronics specialist GigaDevice has introduced a brand new Wi-Fi 6-capable microcontroller household, the GD32VW553 Collection Combo Wi-fi MCU — that includes a processor core primarily based on the free and open RISC-V instruction set structure.
“The brand new GD32VW553 collection, with its optimized RISC-V open-source instruction set structure, incorporates the microcontroller with superior ‘Combo Wi-fi’ connection protocols,” claims GigaDevice’s Eric Jin of the corporate’s launch. “This addresses the growing connectivity calls for within the thriving dwelling home equipment and rising AIoT [Artificial Intelligence of Things] market, reaching a stability between processing efficiency, answer design, and materials prices.”
GigaDevice has launched its first Wi-Fi 6-capable RISC-V chip, the GD32VW553 Collection. (📷: GigaDevice)
The brand new chips are constructed round a single Nuclei Sys N307 processor core, a 32-bit RISC-V implementation operating at as much as 160MHz and with a configurable 32kB instruction cache for improved effectivity. That is mixed with 288kB of static RAM (SRAM) and 32kB of shared SRAM and between 2MB and 4MB of on-chip flash reminiscence, relying on mannequin chosen.
The radio facet of the chip consists of 802.11ax Wi-Fi 6 compatibility, within the 2.4GHz spectrum solely, with a claimed 60 per cent increase to information transmission charges over the corporate’s Wi-Fi 4 (802.11b/g/n) gadgets. It additionally presents Bluetooth 5.2 Low Vitality (BLE) connectivity, providing a 2Mbps high-speed mode and 125/500kbps lower-energy modes. GigaDevice additionally guarantees higher reception in noisy environments by means of a Bundle Visitors Arbitration (PTA) system and help for the Goal Wake Time (TWT) system for improved vitality effectivity.
The chip features a affordable peripherals choice, together with SPI and I2C buses and an analog-to-digital converter (ADC). (📷: GigaDevice)
For {hardware} connectivity, the GD32VW553 consists of as much as 29 general-purpose enter/output (GPIO) pins, three USART, two I2C, one SPI, and one QSPI bus, two 32-bit general-purpose timers, two 16-bit general-purpose timers, 4 16-bit fundamental timers, one superior timer for pulse-width modulation (PMW) help, and a 12-bit analog to digital converter (ADC). The elements run with a 1.8V to three.6V energy enter, with 5V tolerance on the IO pins.
Extra data on the brand new chips is offered on the GigaDevice web site; the corporate has not shared pricing, although its earlier RISC-V elements have been priced extraordinarily competitively.
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